1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for predicting yield parameters based on fault classification.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance.
Semiconductor devices are manufactured from wafers of a semiconducting material. Layers of materials are added, removed, and/or treated during fabrication to create the electrical circuits that make up the device. The fabrication essentially comprises four basic operations. Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
The four operations typically used in the manufacture of semiconductor devices are:                layering, or adding thin layers of various materials to a wafer from which a semiconductor device is produced;        patterning, or removing selected portions of added layers;        doping, or placing specific amounts of dopants in the wafer surface through openings in the added layers; and        heat treatment, or heating and cooling the materials to produce desired effects in the processed wafer.        
Occasionally, during the fabrication process, one or more process steps are not performed as expected on a production wafer. Such conditions may be due to an error in the fabrication facility automated work flow system (e.g., a database or control script error), a tool failure, or an operator error. If the abnormal process steps occur early during the fabrication process, it is not uncommon for the faulty wafer to undergo many subsequent steps prior to the faulty fabrication being identified. Once a fault is identified further processing is often necessary to determine the nature or cause of the fault, unless the fault is grossly obvious. This process is typically referred to as fault classification. Fault classification may be time consuming and may require significant human intervention.
Processing faults have the potential for degrading the performance of the completed devices. In some cases, the device may function at a lower speed, while in other cases, the device may not be functional at all. Referring to FIG. 1, a simplified diagram of a semiconductor wafer 2 is shown. The semiconductor wafer 2 typically includes a plurality of individual semiconductor die 3 arranged in a grid 4. Typically, electrical or functional tests of the semiconductor die are performed to determine their performance capabilities. Usually, these test are not performed until relatively late in the fabrication process. Functional and non-functional devices are identified to determine the overall yield of the wafer 2 based on the results of the final electrical tests. Yield loss can be defined in terms of whether or not all of the submodules that makeup the device on the die 3 are functional. If one of the submodules is not functional, the entire device may die deemed defective. Yield loss can also be driven by degradations in the performance capabilities of the completed devices. For example, a yield loss may be related to the speed of a device due to the consequences of leakage of the device at those process parameters defined based on a deviation between the measured speed and a target speed.
In the fabrication process, hundreds of processes are performed and at every step it is possible that a fault condition may occur. Some of these faults may affect the yield of the device while others may have little or no impact. Until the actual yield is determined through testing performed at the end of the line, it is difficult to determine the impact of the processing faults. In some cases, a wafer that experienced a serious fault may be processed until completion, yet because of the fault's impact on yield, the value of the devices may be less than the cost of completing the processing.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.